Ideally, the filter impulse response should be matched to the pulse shape of the transmitted chips where a chip is defined as one epoch of the PN sequence. The raised cosine pulse shape provides the necessary bandlimiting characteristic in addition to having the property that is exhibits zero intersymbol interference inter-chip interference in this case.
For matched filtering, both the transmit filter and the receiver polyphase filter will have identical square-root raised cosine frequency responses. The filter is designed at a sample rate of 32 samples per chip, for a total of taps. The filter is divided into eight banks of 20 taps each.
Thus, each output is obtained by convolving the input samples with a tap filter. Nine-bit quantization of the coefficients is sufficient for near-ideal performance.
The absolute delays of each bank are listed in Table 3. Each bank has essentially the same frequency response and the response of bank 0 is plotted in FIG.
Discussion of these functions, for example, the boundary conditions of crossing over bank 0 or 7 will be discussed below. A process to simplify the polyphase filtering, downconversion, and despreading operations will now be shown. Assume we are given the following:.
Although not a necessary condition, for the current system it is also assumed that the PN sequence is synchronized with each data symbol, and thus, the N-length PN sequence repeats every symbol. Solving equation 5 in terms of its real and imaginary components, y r and y i , respectively, gives the following sequence:. Next, the complex baseband sequence y n is convolved with a bank of polyphase filter coefficients.
Each bank contains 20 real coefficients, c 0 , c 1 ,. It is noted that here the coefficients for a particular bank have been redesignated c 0 through c 19 for notational simplicity.
It is understood that they are a subset of the original c 0 through c coefficients. The convolution of y with the filter coefficients is given by: EQU4. Equations 7a and 7b each assume that the filter outputs, z n , are computed at a rate of four samples per chip. However it is only necessary to compute a filter output at a rate of two samples per chip. Signals , consist of one sample aligned with the center of each raised cosine pulse the chip detection point per chip and one sample per chip at the chip transition point.
In addition, a demultiplexer coupled with control logic is used to separate the chip transition point samples , from the chip detection point samples , Signals , drive the punctual channel processor , as shown in FIG. Signals , drive both the early channel processor and the late channel processor The sample rate of signals is one sample per chip.
A delay locked loop is used to track the PN sequence timing phase. Consequently, a total of three channel processors , , are required. It is apparent that each convolution operation only involves ten filter coefficients since every other sample of complex baseband signal , is zero.
However, it is simpler to just ignore the sign change and account for it later in the calculation of the delay locked loop error signal in the DSP IC The filter outputs are computed once per chip interval according to the following equations: EQU5. Thus, the coefficients are stored in hardware with the sign of every other coefficient inverted.
The PN sequence, PN , applied to each channel processor , , will have the appropriate delay. Then a data symbol d k can be recovered after despreading and processing by an accumulate and dump filter In the despreading operations of Equations 9 a -9 f below, d p k , d e k , and d 1 k , refer to the complex data symbol , , complex early timing error signal , and complex late timing error signal , outputs associated with the k th data symbol where each output is computed once per data symbol interval.
It is assumed that sample timing adjustments can be made only at symbol boundaries. Normally, timing adjustments are made simply by changing to a new bank of filter coefficients as determined by the sample timing control signal Filter bank zero must then be selected to achieve the proper timing. The two cases are outlined below and show the effects of the polyphase filtering operation. However, there is an additional change that must be considered. The digital downconversion process is not affected by the sample timing shift since it occurs before timing adjustments are made.
But the filtering process is affected. After accounting for the downconversion process, the following is computed:. Note that the convolution operation is the same as in equation 10 above except that the coefficients used for the punctual real and imaginary outputs , have been swapped and the signs of the coefficients now used for the imaginary output have been reversed.
The filter coefficients could be modified to reflect the new changes but it is simpler to leave them unaltered and account for them in the DSP control processor after despreading. The DSP can then just swap real and imaginary symbols , and perform the required sign inversions at the symbol rate. The filter hardware will have to run slightly faster to handle this case. Another approach is to just not compute a filter output until the hardware is ready.
The energy reduction for zeroing the output for one chip interval is negligible, especially for large spread factors. Assuming that timing adjustments do not occur every symbol, the loss is negligible, especially in systems employing forward error correction coding. Thus, the filter hardware is delayed by one sample. In addition, filter bank seven is selected. Similar to advancing the timing phase across a sample boundary, case 1, the filter outputs must be modified. Note that the real and imaginary filter coefficients have been swapped as compared to equation 10 as in case 1 above, but the signs of the coefficients now used for the real output have been reversed.
As in case 1, the DSP IC can just swap real and imaginary symbols , and perform the required sign inversions Thus the filtering and despreading operations do not have to be modified. A specific embodiment of the present invention used to perform the computations symbolized in FIGS. As seen in FIG. Each RAM array stores coefficients for one of the 10 filter taps and supplies a 9-bit operand to its associated multiplier Each RAM array stores eight real coefficients followed by eight imaginary coefficients, corresponding to the eight different filter banks.
A 3-bit bus controls which of the eight filter banks to use, and is steered by timing adjustment control logic. Additional logic must also be provided to advance or retard the input delay line when changing the sample timing phase across a sample boundary. The bit results are added together in a single clock cycle and the result is stored in a bit accumulator The accumulator is large enough that no overflow will occur.
The 8-bit result is latched into one of four output latches , , , It can be seen that the hardware of FIG. Each chip clock phase is offset in time from another by one fourth of a chip period, as can be seen in the timing diagram of FIG.
The sequence of operations performed in one chip clock period are labeled in numerical order in FIG. The labels are defined below:. Compute convolution of delay line with imaginary coefficients. The signals , , , from the I and Q output latches , , , , respectively, drive the early, punctual and late real and imaginary channel processors , , as shown in FIG.
The structure of the PN sequence generator depends on the type of code implemented but is typically constructed with shift registers and Exclusive-Or gates. The PN sequence generator is clocked at the chip rate, but is delayed in increments of one fourth of a chip period before being connected to each successive despreader and drives the early I channel despreader directly. Once acquisition is achieved, the PN timing is fixed and timing tracking is accomplished through the sample timing phase control signal The despreaders The despread outputs are summed in bit accumulators The accumulated sums are latched in tri-state output latches and every data symbol clock i.
The accumulators are also cleared on the same edge of the symbol clock. An accumulator width of sixteen bits is sufficient for spread factors up to without any possibility of overflow. For larger spread factors, scaling and saturation logic must be incorporated into each accumulator. The six output latches can be made addressable so that they can be read over a common data bus. A method and apparatus to perform ideal matched filtering of a spread spectrum signal, assuming that the transmit signal has a square-root raised cosine response, has been outlined.
The method may also be used for cases where matched filtering is not required or necessary. For example, if the spread spectrum transmit signal is unfiltered or is filtered with a full raised cosine filter response, the polyphase receive filter can have any desired lowpass response.
The chip detection process will not be ideal since the polyphase receive filter impulse response is not matched to the transmit spread spectrum signal, but in many cases the loss is less than 1 dB. In addition, the number of filter taps for an equi-ripple lowpass filter is often much less than that required for a square-root raised cosine filter. A polyphase lowpass receive filter can be designed with the characteristics shown in Table 4. Although the filter is not matched to the transmit signal, it still serves to make digital timing corrections and also bandlimits the noise spectrum prior to despreading.
The number of taps has also been significantly reduced and the number of hardware multipliers required for the filtering operation can be reduced from ten to six. The estimated loss in bit error performance for such a receiver structure is less than 1 dB.
The preferred embodiment just described, directed to a single-channel implementation, is readily applicable to another preferred embodiment, which is a multi-channel implementation, yielding a very efficient implementation of a multi-channel direct sequence spread spectrum CDMA receiver. The need for such an implementation can be appreciated with reference to the following. In a CDMA communications system, many portable or mobile transmitters may transmit on the same frequency channel, each with a unique PN spreading sequence.
Often, many geographically separate CDMA transmitters will transmit to a central receiving location such as a CDMA cellular base station or satellite earth station, for connection to the public switched telephone network. In a typical central receiving site, a separate receiver is required to receive each CDMA transmission.
It is assumed that the chip timing frequency and phase of each CDMA transmission are not synchronous, but rather, each remote CDMA transmitter uses its own locally generated chip clock which may have a maximum error tolerance of 1 part per 10 A chip-synchronous CDMA network requires greater complexity and thus higher system costs, especially in a satellite system where the transmission delays can vary more greatly because of the diverse geographic locations of the CDMA transmitters.
Each sampled signal is then downconverted to baseband and despread. However, as shown in FIG. The number of bits of resolution shall be denoted as L. It is possible to posit a relationship of sorts between L and M. In fact, the M-channel polyphase filter embodiment is very similar to that of FIG. The filter coefficients are the same as those used in the single channel case and may have an impulse response matched to the pulse shape of the transmitted chips.
A modulo 2M counter is clocked at a rate of 4M times the chip rate and is used to identify the current channel number, I. The output of the counter is used to address a control RAM , which contains 4-bit values used to address one of the banks of filter coefficients. The 4-bit output of the RAM selects the appropriate filter bank to use for channel I. A control bus from a DSP processor is used to load the contents of the RAM with the 4-bit values mentioned above. However, after the modulo 2M counter has cycled through all 2M counts twice, both I and Q outputs will have been computed for all M channels.
A bank of M delay locked loops in the DSP processor is used to control the timing phase adjustments. When the timing for the i'th channel requires adjustment, the I and Q locations of the i'th channel in the RAM are written over the control bus to indicate the proper coefficients to select.
Note that, for a given state of the delay line , either the I or Q component is calculated. The state machine then can sequence through the control RAM , and I and Q coefficients are automatically selected in the proper sequence.
The final result is latched in output latch Control logic includes a state machine which controls the clocking of the major functional blocks , , , , and of FIG. In addition, the state machine determines the state of each output i.
Output latch performs the functions that latches , , , and perform in the embodiment of FIG. Thus, the data is dealt with one item at a time with a faster clock irrespective of the factor of M , and the latch provides timed outputs accordingly.
In addition, state machine controls the multi-channel despreader hardware shown in FIG. The state machine simultaneously addresses one of 6M bit registers from register file The sum for the proper channel is loaded into the bit accumulator Then the 8-bit data from the output latch is exclusive OR'ed with the selected PN sequence bit and the result is accumulated in accumulator The sum is stored back into the same register previously read in register file A register in the register file is cleared when the first bit of the PN sequence is detected, thus beginning the start of a new data symbol.
The state machine logic contains M status flags which indicate which of the M channels have data available to be read in dual port RAM Normally, the state machine logic advances the PN sequence one bit at a time for each channel. However, whenever the PN chip timing is advanced across a sample boundary for a given channel, the state machine skips one PN sequence location of the RAM Thus, one despread symbol will consist of the sum of N-1 chips instead of the usual N.
Similarly, to retard the PN chip timing across a sample boundary, the state machine will repeat a bit of the PN sequence. It should be noted that the hardware implementation of the multi-channel embodiment just described differs to some extent from the hardware implementation of the single-channel embodiment described earlier.
While some of the details have been omitted for simplicity, those details are well within the abilities of the ordinarily skilled artisan to implement. The magnitude of M is limited primarily by the speed of the digital hardware used.
Greater values of M are possible through greater use of parallelism by implementing multiple polyphase filter and despreader hardware blocks. In light of the above teachings, many modifications in variations of the present invention are possible.
It should be understood, therefore, that the principles of the present invention may be realized in embodiments other than as specifically described herein. What is claimed is: 1. USA en. CAA1 en. TWB en. WOA1 en.
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